1. Field of the Invention
The present invention relates to a liquid crystal device driving circuit, and more specifically, to a circuit for driving a liquid crystal display panel capable of displaying an image with a multiple tone level.
2. Description of Related Art
As a liquid crystal device driving circuit for generating a source voltage driving a liquid crystal display panel typified by an active matrix type, a circuit for enabling a multiple tone or gray scale image on the order of eight gray scale levels has been implemented in the form of a LSI (large scale integrated circuit) and is now under mass production and widely used.
FIG. 1 is a block diagram showing one example of a conventional liquid crystal device driving circuit. In order to display a multiple gray scale image in a liquid crystal display panel, it is required to supply a drive voltage corresponding to a required luminance, from drive voltage output terminals T1 to Tk of a transistor switch circuit 3 to corresponding source lines of the liquid crystal display panel.
For this purpose, the drive circuit includes "k" stages of "n"-bit shift registers 15a to 15k receiving an image input data Vi from an image data input terminal, a corresponding number of "n"-bit latches 16a to 16k each for latching the "n"-bit data of a corresponding one of the "n"-bit shift registers 15a to 15k, and a corresponding number of selector circuits 14a to 14k for selectively turning on output transistors Q11 to Qmk included in the transistor switch circuit 3 on the basis of an output of the latches 16a to 16k.
Namely, an "n"-bit digital image input data Vi indicative of "m" gray scale levels is supplied from the image data input terminal 7, and shifted and stored in the "n"-bit shift registers 15a to 15k in response to a clock pulse Vc applied to a clock input terminal 1. In response to a latch pulse Vr applied to a latch pulse input terminal 2, the data stored in each of the registers is transferred to a corresponding one of the "n"-bit latches 16a to 16k.
The "n"-bit data latched in each latch is decoded by a corresponding one of the selector circuits 14a to 14k to the effect that one transistor of the first "m" output stage transistors Q11 to Qm1 connected to the drive output terminal T1 of the transistor switch circuit 3 is turned on, and one transistor of the "k"th "m" output stage transistors Q1k to Qmk connected to the drive output terminal Tk is turned on. With this arrangement, voltages V1, V2, . . . , V.sub.m corresponding to drain voltage terminals 8a to 8m of "m" gray scale levels are supplied, so that voltages of "m" gray scale levels are supplied to an external liquid crystal display.
For example, assuming that the image input data Vi is composed of digital signals D.sub.0, D.sub.1, . . . , D.sub.n-1, the voltage Vo appearing on the drive output terminal T1 is as shown in FIG. 2.
In this conventional liquid crystal device driving circuit, if the number of gray scale levels is increased, it is required to connect low-impedance large-current-capacity, external voltage supplies, and therefore, when the driving circuit is assembled in the liquid crystal display panel, wiring conductors must be thickened and the overall assembly of the liquid crystal display panel correspondingly becomes Large. In addition, with an increase in the number of pixels in the liquid crystal display panel, the driving circuit is required to have a low impedance.
Furthermore, if the number of gray scale levels is increased, when a buffer circuit having a low impedance and a large output capacity is implemented on the same semiconductor substrate, the chip size becomes extremely large, and therefore, the driving circuit becomes costly. Because of this reason, most of this type of liquid crystal display driver is on the order of 8 gray scale levels to 16 gray scale levels. For a full-color display, however, the liquid crystal display panel required to have a gray scale of 64 levels or more is going to be marketed.
Under this circumstance, in order to increase the number of gray scale levels, the present applicant has proposed one approach, which is disclosed in the specification of Japanese Patent Application No. Hei 4-80176. This approach is featured, not only by turning on only one of the transistors Q.sub.11 to Q.sub.m1 of the transistor switch circuit as in the circuit shown in FIG. 1, but also by simultaneously turning on a plurality of transistors of the transistors Q.sub.11 to Q.sub.m1, so that the voltage outputted from the drive voltage output terminal T1 has a multiple voltage level.
FIG. 3 is a block diagram of this liquid crystal display driving circuit, and in FIG. 3, the elements similar to those shown in FIG. 1 are given the same Reference Numerals.
For this purpose, the drive circuit includes "k" stages of "(n+1)"-bit shift registers 5a to 5k receiving an image input data from an image data input terminal 7, a corresponding number of "(n+1)"-bit latches 6a to 6k each for latching the "(n+1)"-bit data of a corresponding one of the "(n+1)"-bit shift registers 5a to 5k, and a corresponding number of selector circuits 4a to 4k for selectively turning on output transistors Q11 to Qmk included in the transistor switch circuit 3 by decoding the data outputted from the latches 5a to 6k. With a selective turning-on control of the transistors Q11 to Qmk in the transistor switch circuit 3, a drive output voltage Vo is generated on each of the drive voltage output terminals T.sub.1 to T.sub.k.
Namely, a digital image input data Vi formed of "(n+1)" bits (D.sub.0, D.sub.1, . . . , D.sub.n) is supplied from the input terminal 7, and sequentially shifted and stored in the "(n+1)"-bit shift registers 5a to 5k in response to a clock pulse Vc. In response to a latch pulse Vr, the data stored in each of the registers is transferred to a corresponding one of the "(n+1)"-bit latches 6a to 6k. The "(n+1)"-bit data latched in each latch is decoded by a corresponding one of the selector circuits 4a to 4k to the effect that either one transistor or two transistors of the first "m" output stage transistors Q11 to Qm1 connected to the drive output terminal T1 of the transistor switch circuit 3 is simultaneously turned on, and either one transistor or two transistors of the "k"th "m" output stage transistors Q1k to Qmk connected to the drive output terminal Tk is simultaneously turned on. With this arrangement, voltages V1, V2, . . . , V.sub.m corresponding to drain voltage terminals 8a to 8m of "m" gray scale levels or their combined voltages are generated.
For example, assuming that the "(n+1)"-bit image input data Vi is composed of digital signals D.sub.0, D.sub.1, . . . , D.sub.n, the voltage Vo appearing on the drive output terminal T1 is as shown in FIG. 4.
Here, when the digital signals (D.sub.0, D.sub.1, . . . , D.sub.n)=(0, 0, . . . , 0), only the output transistor Q.sub.11 is turned on by the associated selector circuit 4a, so that the output voltage V.sub.1 is outputted. When the digital signals (D.sub.0, D.sub.1, . . . , D.sub.n)=(0, 0, . . . , 1), the output transistors Q.sub.11 and Q.sub.21 are simultaneously turned on by the associated selector circuit 4a. At this time, assuming that all the output transistors Q.sub.11 to Q.sub.mk have the same current driving capacity, the output voltage Vo becomes Vo=(V.sub.1 +V.sub.2)/2.
Namely, the output transistors are equally formed on the same silicon substrate, the characteristics of the output transistors Q.sub.11 to Q.sub.mk have only a little variation in a relative small zone within the same chip, even if it greatly varies from one manufacturing lot to another and from one wafer to another. Namely, the variation of the transistors is on the order of 10% at maximum. Therefore, it becomes Vo.apprxeq.(V.sub.1 +V.sub.2)/2, depending on a ratio in on-resistance ratio of the output transistors Q.sub.11 and Q.sub.21. Furthermore, in order to realize a multiple gray scale level in the liquid crystal display panel, the intervals of voltage steps are obtained by dividing the voltage of about 3 V to 4 V applied to the liquid crystal display, by the number of required gray scale levels.
For example, if 16 gray scale levels are required, the voltage steps having the voltage intervals on the order of 0.25 V (=4 V/16) are applied to the liquid crystal display panel. Accordingly, assuming that when the output transistors Q.sub.11 and Q.sub.21 are simultaneously turned on, a relative variation between the output transistors Q.sub.11 and Q.sub.21 is 10%, if (V.sub.1 -V.sub.2)=0.25 V, the variation of the output voltage Vo is on the order of 25 mV. This is not so significant in an image displayed on the liquid crystal display panel.
Similarly, either one or two of each "m" transistors of the output transistors Q.sub.1k to Q.sub.mk are simultaneously turned on by the associated selector circuit 4k. Thus, (2m-1) different output drive voltages can be obtained from the "m" different voltages Vm supplied from the voltage supply terminals 8a to 8m.
Incidentally, for convenience, the switching elements of the transistor switch circuit 3 have been composed of the transistors Q.sub.11 to Q.sub.mk. However, even if the transistors are replaced with transfer gates, the same effect can be obtained.
In the above mentioned liquid crystal device driving circuit, when the output transistors Q.sub.11 and Q.sub.21 are simultaneously turned on, since the output impedance of the output transistors Q.sub.11 and Q.sub.mk is on the order of about 10K.OMEGA. to about 5K.OMEGA., the current flowing through each output becomes on the order of about 50 .mu.A to about 25 .mu.A (=0.25 V/10K.OMEGA. to 0.25 V/5K.OMEGA.. In an LCD driver LSI in which a driving circuit for the liquid crystal display panel is formed on a silicon substrate, in the case of the output number "k"=192, the current becomes 4.8 mA to 9.6 mA, and therefore, the consumed electric power correspondingly becomes 1.2 mW to 2.4 mW (=(4.8 mA to 9.6 mA).times.0.25 V). This value is almost no problem as the LCD driver LSI.
However, the liquid crystal panel uses at least 10 LCD driver LSIs each having the 192 outputs, and therefore:, a voltage supply for the liquid crystal device driving circuit requires at least a current corresponding to the 10 LCD driver LSIs, namely, a current supplying capacity of 48 mA to 96 mA. If the voltage supply is 20 V, there is required a large consumed electric power of 0.96 W to 1.92 W (=(48 mA to 96 mA).times.20 V).
Furthermore, the conventional liquid crystal device driving circuit can realize the (2m-1) gray scale levels, by simultaneously turning on any two transistors of each "m" transistors of the output transistors Q.sub.1k to Q.sub.mk by action of the selector circuit 4k. However, if the potential difference between the simultaneously turned-on transistors is large, a very large current is required for the conventional liquid crystal device driving circuit, and therefore, the consumed electric power correspondingly becomes large. This is not practical.